The present invention relates to a standard cell for a plurality of power supplies and technologies related thereto.
In recent years, the ever-increasing speed, integration and size of the semiconductor integrated circuits has led to the current use of a layout design using a standard cell library. On the other hand, the increased speed and integration of circuits have raised the problem of power consumption. The clock tree portion of the circuit attains large proportions of power consumption, and therefore the power consumption of the clock tree portion is required to be decreased.
As shown in FIG. 1, the standard cell (hereinafter sometimes referred to as the cell) of a standard cell library is configured of a power line 101, a grounding line 102, a transistor gate 103, an N well 104, a P well 105, a P-channel diffusion region 106 and an N-channel diffusion region 107.
In the case where two cell rows are arranged in the same direction as shown in FIG. 2A, all of the power lines 101 are located at the upper position, all of the grounding lines 102 are located at the lower position, and the two cell rows are separated from each other. In the case where the two cell rows are arranged in opposite directions with the power lines 101 at the central position and the grounding lines 102 at the top and bottom positions as shown in FIG. 2B, on the other hand, the N wells 104 of the two cell rows are in contact with each other. In this case, the two cell rows are not required to be separated from each other so that the area of the block can be reduced.
In a clock tree shown in FIG. 3, the clock signal is applied from a first clock buffer 202 at the center to a plurality of second clock buffers 203 radially arranged with equal distances. Further from the second clock buffers 203, the clock signal is supplied in radial direction synchronously to a plurality of flip-flops 201 with equal distances. By reducing the source voltage of the clock tree portion below that of the logic circuit portion, the power consumption of the clock tree portion can be reduced without reducing the operating frequency of the circuit.
In the circuit configuration shown in FIG. 4, the only requirement for the clock tree portion 204 including the first and second clock buffers 202, 203 is to maintain the synchronism of the clock signals. In view of this, only the clock tree portion 204 is reduced in voltage as compared with the supply potential to a circuit element string 205 including the flip-flops 201, 201. In this way, the power consumption for the whole circuit is reduced while securing the operating speed of the circuit element string 205.
Presence of the cell operating at different power voltages causes the short-circuit between the power line 101 and a water. This requires separation of the circuit-element string 205 corresponding to the power voltage.
In the case where the flip-flops and the clock buffers are arranged in different rows in the block, however, the distance is lengthened between the flip-flops and the clock buffers depending on the arrangement of the flip-flops. As a result, the wiring delay is increased, thereby posing the problem that the clock signals are undesirably input to the flip-flops at different timings.
Another problem is that the cell region of the clock buffers and the cell region of the logic circuit are required to be prepared separately from each other. This poses the problem of an increased block area.
The Japanese Unexamined Patent Publication No. 10-284609 discloses a technique in which a plurality of types of power lines having different source voltages are used in the case where there coexist a plurality of types of cells having different operating voltages in the same string.
In FIG. 5, the cells in an even-numbered row and an odd-numbered row are arranged in opposite directions provisionally so that the N wells of adjacent rows are kept in contact with each other. Even in the case where a standard cell Un (hereinafter referred to as the single-power-supply cell) for a single power supply and a standard cell Cp for a plurality of power supplies (hereinafter referred to as the plural-power-supply cell) are adjacent to each other in a vertical direction, the N well of the single power cell Un1 is contact with the N well of the plural-power-supply cell Cp. In view of the fact that the potential applied to the N well of the single-power-supply cell Un is different from the potential applied to the N well of the plural-power-supply cell Cp, however, a current flows and the potential of the N well of the plural-power-supply cell Cp undergoes a change. As a result, the source voltage is differentiated from the substrate voltage, so that the threshold voltage of the transistor changes and so does the operating speed thereof. In order to avoid this inconvenience, the cells in the upper row and the cells in the lower row are required to be arranged in spaced relation with each other. However, this raises the problem of an increased block area.
Also, the well is an independent entity in the cell, and the cell area is so small that a large substrate contact cannot be secured in the microprocessing, resulting in the problem that a sufficient latch-up strength cannot be obtained.
Accordingly, it is an main object of this invention to provide a technique for laying out a semiconductor integrated circuit having a plurality of source voltages without increasing the area of the block and provide a means for cutting the consumption power of the clock tree portion.
Other objects, features and advantages of the invention will be made apparent from the description below.
In order to solve the problem described above, according to a first aspect of the invention, there is provided a standard cell for a plurality of power supplies (hereinafter referred to as the plural-power-supply cell), comprising a first power line, a second power line isolated electrically from the first power line, an N well arranged in spaced relation with the whole periphery of the boundaries of the cell, a grounding line and a P well arranged in contact with the boundaries on both sides in the direction along the power lines of the cell (hereinafter sometimes referred to as the power-line direction) (FIG. 6).
With this configuration, even in the case where standard cells (hereinafter referred to as the cells) of different source voltages are arranged on the same row, the use of the first power line and the second power line makes it possible to arrange different power lines in isolation from each other. Further, even in the case where the cells are arranged adjacently to each other in the power-line direction or the direction orthogonal thereto, the N well of a plural-power-supply cell can be isolated from the N wells of adjacent cells (FIG. 9).
According to a second aspect of the invention, the second power line is formed in contact with the two boundaries along the power-line direction of the cell.
With this configuration, in the case where the plural-power-supply cells are arranged adjacently to each other, the first power lines and the second power lines of the cells can be connected to each other thereby to form a series of first power lines and a series of second power lines (FIG. 7).
According to a third aspect of the invention, the N well is electrically connected to the second power line, and the P well is electrically connected to the grounding line.
With this configuration, the second power line is connected to a power supply point of a semiconductor integrated circuit and the grounding line to the grounding point of the semiconductor integrated circuit, thereby making it possible to apply the source potential to the N well and the grounding potential to the P well.
According to a fourth aspect of the invention, the N well is electrically connected to the first power line or the second power line by a wiring or a contact.
With this configuration, in the wiring step corresponding to the last half of the fabrication process, the potential application to the N well in the cell can be switched between the first power line and the second power line. As a result, the requirement for a specification change involving a high-speed specification or a low-speed specification accompanied by a significant design change can be met faster than the original design for a faster fabrication process (FIG. 12).
According to a fifth aspect of the invention, the plural-power-supply cell has a decoupling capacitor connected to the second power line.
With this configuration, the power noise of the second power line can be suppressed by the decoupling capacitor (FIG. 13).
According to a sixth aspect of the invention, the plural-power-supply cell further has a third power line.
With this configuration, the potential application to the N well of the plural-power-supply cell can be switched between the first, second and third power lines in the wiring step (FIG. 18).
According to a seventh aspect of the invention, the plural-power-supply cell further has a second N well arranged at the two ends along the direction of the power lines of the cell.
With this configuration, the second N well of the plural-power-supply cell is in contact with the N well of a standard cell for a single power supply (hereinafter referred to as the single-power-supply cell) adjacent to the plural-power-supply cell, and therefore the area of the N well in the single-power-supply cell can be increased. Also two circuits of different source voltages can be secured in the cell (FIGS. 14, 15).
According to an eighth aspect of the invention, the second N well is electrically connected with the first power line.
With this configuration, a power potential can be applied to the second well by connecting the first power line to the power supply point of the semiconductor integrated circuit.
According to a ninth aspect of the invention, the plural-power-supply cell further has a third N well arranged in spaced relation with the boundaries on both sides along the power lines of the cell.
With this configuration, the plural-power-supply cell can have three circuits of different source voltages therein.
According to a tenth aspect of the invention, a standard cell library (hereinafter referred to as the library) comprising a first power line and a second power line electrically isolated from the first power line, an N well arranged in spaced relation with the boundaries on both sides along the direction orthogonal to the power lines of the cell, a grounding line and a P well arranged in contact with the boundaries on both sides along the direction of the power lines, wherein the standard cell library consists of a first cell including the N well arranged in spaced relation with the boundaries on both sides along the direction of the power lines of the cell, and a second cell including an N well arranged in contact with an end or the other end or the two ends along the direction of the power lines of the cell.
With this configuration, in the case where plural-power-supply cells are arranged adjacently to each other, the N wells of the plural-power-supply cells can be arranged in contact with each other by replacing the plural-power-supply cells with those having the N wells in contact with the boundary (FIGS. 16, 17(a) and 17(b).
According to an 11th aspect of the invention, the library for a standard cell constitutes a plural-power-supply cell combined with a single-power-supply cell, wherein the plural-power-supply cell includes a first power line, a second power line electrically isolated from the first power line, an N well arranged in spaced relation with the whole periphery of the cell boundaries, a grounding line and a P well arranged in contact with the boundaries on both sides along the direction of the power lines, and wherein the single-power-supply cell includes a first power line, an N well arranged in contact with the boundaries on both sides along the direction of the power lines, a grounding line and a P well arranged in contact with the boundaries on both sides along the direction of the power lines.
With this configuration, the plural-power-supply cells and the single-power-supply cells can be used together in the same block, and by differentiating the source potential applied to the first power line from the source potential applied to the second power line, the cells operating at a plurality of source voltages can coexist in the same circuit (FIG. 6 for the plural-power-supply cell, FIG. 8 for the single-power-supply cell, and FIGS. 9, 11 for the cell combination).
According to a 12th aspect of the invention, the plural-power-supply cell has a height an integer multiple of the height of the single-power-supply cell.
With this configuration, a larger area of the N-well region of the plural-power-supply cell can be secured than in the case where the plural-power-supply cell has the same height as the single-power-supply cell. Thus, the circuit can be laid out easily in spite of the coexistence of the single-power-supply cell and the plural-power-supply cell in the circuit (FIGS. 10, 11).
According to a 13th aspect of the invention, in the method of wiring power supplies, a power strap wiring is prepared using a first wiring layer and the second power line of the plural-power-supply cell and the power strap wiring are connected to each other using a second wiring layer.
With this configuration, even in the case where a single-power-supply cell and a plural-power-supply cell are existent within the same row, the power supply of the second power line can be wired by connecting the second power line of the plural-power-supply cell to the power strap wiring (FIGS. 20).
According to a 14th aspect of the invention, in the method of wiring power supplies, a plurality of power strap wirings are prepared using the first wiring layer, and the second power line of the plural-power-supply cell and the plurality of power strap wirings are connected to each other using the second wiring layer, the keyword being xe2x80x9ca plurality of the power strap wiringsxe2x80x9d.
With this configuration, even in the case where a single-power-supply cell and a plural-power-supply cell are existent within the same row, the power supply of the second power line can be wired by connecting the second power line of the plural-power-supply cell to a plurality of the power strap wirings. In view of the fact that the second power line of the plural-power-supply cell is connected to a plurality of the power strap wirings, the source voltage drop of the second power line can be suppressed by reducing the wiring resistance of the second power line (FIG. 21).
According to a 15th aspect of the invention, in the method of wiring power supplies, a power strap wiring is prepared using a first wiring layer, and a partial wiring connected with the second power lines of a plurality of the plural-power-supply cells is connected to the power strap wiring using a second wiring layer, the keyword being xe2x80x9cthe partial wiringxe2x80x9d.
With this configuration, the second power lines of the plural-power-supply cells existent in different rows can be formed into a single wiring (partial wiring) and connected to the power strap wiring. Thus, the second power lines can be wired with small wiring resources (FIG. 22).
According to a 16th aspect of the invention, in the method of wiring power supplies, a plurality of power strap wirings are prepared using the first wiring layer, and a partial wiring connected with the second power lines of a plurality of the plural-power-supply cells is connected to a plurality of the power strap wirings using the second wiring layer, the keywords being xe2x80x9ca plurality of the power strap wirings and the partial wiringxe2x80x9d.
With this configuration, the second power lines of the plural-power-supply cells existing in different rows can be connected to the power strap wiring collectively into a single wiring (partial wiring). As a result, the second power lines can be wired with small wiring resources. Also, in view of the fact that the second power lines are connected with a plurality of the power strap wirings, the source voltage drop of the second power lines can be suppressed by reducing the wiring resistance of the second power lines.
According to a 17th aspect of the invention, in the method of wiring power supplies, the power strap wiring is arranged in such a manner that the shortest distance from the power strap wiring to the plural-power-supply cell is not more than a predetermined value after arranging the plural-power-supply cell, the keywords being xe2x80x9cafter arranging the plural-power-supply cellxe2x80x9d and xe2x80x9cthe shortest distancexe2x80x9d.
With this configuration, the shortest distance from the power strap wiring to the plural-power-supply cell can be controlled, so that the source voltage drop of the second power line can be suppressed by reducing the wiring resistance of the second power line (FIGS. 23, 24).
According to an 18th aspect of the invention, in the method of wiring power supplies, the power strap wiring is arranged in such a manner that the resistance value from the power strap wiring to the plural-power-supply cell is not more than a predetermined value after arranging the plural-power-supply cell, the keywords being xe2x80x9cafter arranging the plural-power-supply cellxe2x80x9d and xe2x80x9cthe resistance valuexe2x80x9d.
With this configuration, the resistance value of the wiring from the power strap wiring to the plural-power-supply cell can be controlled, so that the source voltage drop of the second power line can be suppressed by reducing the wiring resistance of the second power line (FIGS. 23, 24).
According to a 19th aspect of the invention, in the method of wiring power supplies, the power strap wiring is arranged in such a manner that the source voltage drop value from the power strap wiring to the plural-power-supply cell is not more than a predetermined value after arranging the plural-power-supply cell, the keywords being xe2x80x9cafter arranging the plural-power-supply cellxe2x80x9d and xe2x80x9cthe source voltage drop valuexe2x80x9d.
With this configuration, the source voltage drop value from the power strap wiring to the plural-power-supply cell can be controlled so that the source voltage drop across the second power line can be suppressed (FIGS. 23, 24).
According to a 20th aspect of the invention, in the method of wiring power supplies, the plural-power-supply cell is arranged in such a manner that the shortest distance from the power strap wiring to the plural-power-supply cell is not more than a predetermined value after arranging the power strap wiring, the keywords being xe2x80x9cafter arranging the power strap wiringxe2x80x9d and xe2x80x9cthe shortest distancexe2x80x9d.
With this configuration, the shortest distance from the power strap wiring to the plural-power-supply cell can be decreased, so that the source voltage drop of the second power line can be suppressed by reducing the wiring resistance of the second power line (FIGS. 25, 26).
According to a 21st aspect of the invention, in the method of wiring power supplies, the plural-power-supply cell is arranged in such a manner that the resistance value from the power strap wiring to the plural-power-supply cell is not more than a predetermined value after arranging the power strap wiring, the keywords being xe2x80x9cafter arranging the power strap wiringxe2x80x9d and xe2x80x9cthe resistance valuexe2x80x9d.
With this configuration, the resistance value of the wiring from the power strap wiring to the plural-power-supply cell can be controlled, so that the source voltage drop of the second power line can be suppressed by reducing the wiring resistance of the second power line (FIGS. 25, 26).
According to a 22nd aspect of the invention, in the method of wiring power supplies, the plural-power-supply cell is arranged in such a manner that the source voltage drop value from the power strap wiring to the plural-power-supply cell is not more than a predetermined value after arranging the power strap wiring, the keywords being xe2x80x9cafter arranging the power strap wiringxe2x80x9d and xe2x80x9cthe source voltage drop valuexe2x80x9d.
With this configuration, the source voltage drop value from the power strap wiring to the plural-power-supply cell can be controlled thereby to suppress the source voltage drop of the second power line (FIGS. 25, 26).
According to a 23rd aspect of the invention, in the semiconductor integrated device, the plural-power-supply cell is used for the clock tree portion.
With this configuration, the source voltage of the clock tree portion can be changed by changing the source potential applied to the second power line (FIG. 27).
According to a 24th aspect of the invention, in the semiconductor integrated device, the plural-power-supply cell is used for the clock tree portion, and the potential of the second power line of the plural-power-supply cell is decreased below the potential of the first power line.
With this configuration, the source voltage of the cell of the clock tree portion can be changed, so that the power consumption of the clock tree can be reduced by decreasing the source voltage of the clock tree portion (FIG. 27).
According to a 25th aspect of the invention, in the semiconductor integrated device, the clock tree portion is connected to a latch, and the last stage of the clock tree portion makes up a pulse generating circuit.
With this configuration, the source voltage of the cell of the clock tree portion can be changed, so that the power consumption of the clock tree can be reduced by decreasing the source voltage of the clock tree portion. Also, the power consumption of the block as a whole can be further reduced by a flip-flop made up of a pulse generating circuit and a latch (FIG. 28).
According to a 26th aspect of the invention, in the semiconductor integrated device, the plural-power-supply cell is used for a circuit element string portion deficient of the operating speed.
With this configuration, the source voltage of the circuit element string portion deficient of the operating speed can be changed by changing the source potential supplied to the second power line.
According to a 27th aspect of the invention, in the semiconductor integrated device, the plural-power-supply cell is used for a circuit element string portion deficient of the operating speed, and the potential of the second power line of the plural-power-supply cell is increased beyond the potential of the first power line.
With this configuration, the source voltage of the circuit element string portion deficient of the operating speed can be changed, so that the operating speed of the circuit element string can be increased by increasing the source voltage of the circuit element string (FIG. 32).
According to a 28th aspect of the invention, in the semiconductor integrated device, the plural-power-supply cell is used for the circuit element string portion having a margin of the operating speed.
With this configuration, the source voltage of the circuit element string portion having a margin of the operating speed can be changed by changing the source potential applied to the second power line.
According to a 29th aspect of the invention, in the semiconductor integrated device, the plural-power-supply cell is used for the circuit element string portion having a margin of the operating speed, and the potential of the second power line of the plural-power-supply cell is reduced below the potential of the first power line.
With this configuration, the source voltage of the circuit element portion having a margin of the operating speed can be changed. Also, the power consumption of the circuit element string can be reduced by decreasing the source voltage of the circuit element portion having a margin of the operating speed.
According to a 30th aspect of the invention, the semiconductor integrated device comprises a first cell having a large peak current and a second cell having a small peak current, and the plural-power-supply cell is used as the cell having a large peak current.
With this configuration, the propagation of the power noises due to the cell having a large peak current to the cell having a small peak current can be suppressed.
The foregoing and other aspects will become apparent from the following description of the invention when considered in conjunction with the accompanying drawing figures.